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ultrafast sige ecl clock/data buffers ADCLK905/adclk907/adclk925 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 95 ps propagation delay 7.5 ghz toggle rate 60 ps typical output rise/fall 60 fs random jitter (rj) on-chip terminations at both input pins extended industrial temperature range: ?40c to +125c 2.5 v to 3.3 v power supply (v cc ? v ee ) applications clock and data signal restoration and level shifting automated test equipment (ate) high speed instrumentation high speed line receivers threshold detection converter clocking general description the ADCLK905 (one input, one output), adclk907 (dual one input, one output), and adclk925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the analog devices, inc., proprietary xfcb3 silicon germanium (sige) bipolar process. the ADCLK905/adclk907/adclk925 feature full-swing emitter coupled logic (ecl) output drivers. for pecl (positive ecl) operation, bias v cc to the positive supply and v ee to ground. for necl (negative ecl) operation, bias v cc to ground and v ee to the negative supply. the buffers offer 95 ps propagation delay, 7.5 ghz toggle rate, 10 gbps data rate, and 60 fs random jitter (rj). the inputs have center tapped, 100 , on-chip termination resistors. a v ref pin is available for biasing ac-coupled inputs. the ecl output stages are designed to directly drive 800 mv each side into 50 terminated to v cc ? 2 v for a total differential output swing of 1.6 v. the ADCLK905/adclk907/adclk925 are available in 16-lead lfcsp packages. typic al application circuits d d q v cc v ee v t q v ref 06318-001 figure 1. ADCLK905 ecl 1:1 clock/data buffer d1 d1 q1 v cc v ee v t 1 q1 v ref 1 d2 q2 v cc v ee v t 2 d2 v ref 2 q2 06318-002 figure 2. adclk907 ecl dual 1:1 clock/data buffer d d v cc v ee v t v ref q1 q1 q2 q2 06318-003 figure 3. adclk925 ecl 1:2 clock/data fanout buffer
ADCLK905/adclk907/adclk925 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 typi cal application circuit s........................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics............................................................. 3 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 esd caution.................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ..............................................8 applications information .............................................................. 11 power/ground layout and bypassing..................................... 11 output stages ............................................................................... 11 optimizing high speed performance ..................................... 11 buffer random jitter.................................................................. 11 typical application circuits ......................................................... 12 evaluation board schematic ......................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 8/07revision 0: initial version
ADCLK905/adclk907/adclk925 rev. 0 | page 3 of 16 specifications electrical characteristics typical (typ) values are given for v cc ? v ee = 3.3 v and t a = 25c, unless otherwise noted. minimum (min) and maximum (max) values are given over the full v cc ? v ee = 3.3 v 10% and t a = ?40c to +125c variation, unless otherwise noted. table 1. parameter symbol min typ max unit conditions dc input characteristics input voltage high level v ih v ee + 1.6 v cc v input voltage low level v il v ee v cc ? 0.7 v input differential range v id 0.2 3.4 v p-p ?40c to +85c (1.7 v between input pins) v id 0.2 2.8 v p-p 85c to 125c (1.4 v between input pins) input capacitance c in 0.4 pf input resistance, single-ended mode 50 input resistance, differential mode 100 input resistance, common mode 50 k open v t input bias current 20 a dc output characteristics output voltage high level v oh v cc ? 1.26 v cc ? 0.76 v 50 to (v cc ? 2.0 v) output voltage low level v ol v cc ? 1.99 v cc ? 1.54 v 50 to (v cc ? 2.0 v) output voltage differential v od 610 1040 mv 50 to (v cc ? 2.0 v) reference voltage v ref output voltage (v cc + 1)/2 v ?500 a to +500 a output resistance 250 ac performance propagation delay t pd 70 95 125 ps v cc = 3.3 v 10%, v icm = v ref , v id = 0.5 v p-p 70 95 125 ps v cc = 2.5 v 5%, v icm = v ref , v id = 0.5 v p-p propagation delay temperature coefficient 50 fs/c propagation delay skew (output to output) adclk907 15 ps v id = 0.5 v propagation delay skew (output to output) adclk925 10 ps v id = 0.5 v propagation delay skew (device to device) 35 ps v id = 0.5 v toggle rate 6 7.5 ghz >0.8 v differential output swing, v cc = 3.3 v 10% 6.5 ghz >0.8 v differential output swing, v cc = 2.5 v 5% random jitter rj 60 fs rms v id = 1600 mv, 8 v/ns, v icm = 1.85 v rise/fall time t r /t f 30 85 ps 20%/80% additive phase noise 622.08 mhz ?138 dbc/hz @10 hz offset ?144 dbc/hz @100 hz offset ?152 dbc/hz @1 khz offset ?159 dbc/hz @10 khz offset ?161 dbc/hz @100 khz offset ?161 dbc/hz >1 mhz offset 122.88 mhz ?135 dbc/hz @10 hz offset ?145 dbc/hz @100 hz offset ?153 dbc/hz @1 khz offset ?160 dbc/hz @10 khz offset ?161 dbc/hz @100 khz offset ?161 dbc/hz >1 mhz offset
ADCLK905/adclk907/adclk925 rev. 0 | page 4 of 16 parameter symbol min typ max unit conditions power supply supply voltage requirement v cc ? v ee 2.375 3.63 v 2.5 v ? 5% to 3.3 v + 10% power supply current static ADCLK905 negative supply current i vee 24 ma v cc ? v ee = 2.5 v 25 40 ma v cc ? v ee = 3.3 v 10% positive supply current i vcc 47 ma v cc ? v ee = 2.5 v 48 63 ma v cc ? v ee = 3.3 v 10% adclk907 negative supply current i vee 48 ma v cc ? v ee = 2.5 v 50 80 ma v cc ? v ee = 3.3 v 10% positive supply current i vcc 94 ma v cc ? v ee = 2.5 v 96 126 ma v cc ? v ee = 3.3 v 10% adclk925 negative supply current i vee 29 ma v cc ? v ee = 2.5 v 31 51 ma v cc ? v ee = 3.3 v 10% positive supply current i vcc 76 ma v cc ? v ee = 2.5 v 77 97 ma v cc ? v ee = 3.3 v 10% power supply rejection 1 psr vcc 3 ps/v v cc ? v ee = 3.0 v 20% output swing supply rejection 2 psr vcc 26 db v cc ? v ee = 3.0 v 20% 1 change in t pd per change in v cc . 2 change in output sw ing per change in v cc .
ADCLK905/adclk907/adclk925 rev. 0 | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltage v cc ? v ee 6.0 v input voltage d (d1, d2), d ( d1 , d2 ) v ee ? 0.5 v to v cc + 0.5 v d1, d2, d1 , d2 to v t pin (cml or pecl termination) 40 ma d (d1, d2) to d ( d1 , d2 ) 1.8 v maximum voltage on output pins v cc + 0.5 v maximum output current 35 ma input termination, v t to d (d1, d2), d ( d1 , d2 ) 2 v voltage reference, v ref v cc ? v ee temperature operating temperature range, ambient ?40c to +125c operating temperature, junction 150c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 16-lead lfcsp 70 c/w esd caution
ADCLK905/adclk907/adclk925 rev. 0 | page 6 of 16 pin configurations a nd function descriptions pin 1 indicator nc = no connect 1d 2d 3 nc 4 nc 11 q 12 q 10 nc 9nc 5 n c 6 n c 7 v e e 8 v c c 1 5 v r e f 1 6 v t 1 4 v e e 1 3 v c c ADCLK905 top view (not to scale) 06318-004 figure 4. ADCLK905 pin configuration table 4. pin function descriptions for 1:1 ADCLK905 buffer pin no. mnemonic description 1 d noninverting input. 2 d inverting input. 3, 4, 5, 6, 9, 10 nc no connect. no physical connection to the die. 7, 14 v ee negative supply voltage. 8, 13 v cc positive supply voltage. 11 q inverting output. 12 q noninverting output. 15 v ref reference voltage. reference voltage for biasing ac-coupled inputs. 16 v t center tap. center tap of 100 input resistor. heat sink nc no connect. the metallic back surface of the package is no t electrically connected to any part of the circuit. it can be left floating for optimal electrical isolation between the package handle and the substrate of the die. it can also be soldered to the application board if improved thermal and/or mechanical stability is desired. exposed metal at the corners of the package is connected to this back surface. allow sufficient clearance to vias and other components. pin 1 indicator 1 d1 2 d1 3 d2 4 d2 11 q1 12 q1 10 q2 9q2 5 v t 2 6 v r e f 2 7 v e e 8 v c c 1 5 v r e f 1 1 6 v t 1 1 4 v e e 1 3 v c c adclk907 top view (not to scale) 06318-005 figure 5. adclk907 pin configuration table 5. pin function descriptions for dual 1:1 adclk907 buffer pin no. mnemonic description 1 d1 noninverting input 1. 2 d1 inverting input 1. 3 d2 noninverting input 2. 4 d2 inverting input 2. 5 v t 2 center tap 2. center tap of 100 input resistor, channel 2. 6 v ref 2 reference voltage 2. reference voltage for biasing ac-coupled inputs, channel 2. 7, 14 v ee negative supply voltage. 8, 13 v cc positive supply voltage. pin 8 and pin 13 are not strapped internally. 9 q2 inverting output 2.
ADCLK905/adclk907/adclk925 rev. 0 | page 7 of 16 pin no. mnemonic description 10 q2 noninverting output 2. 11 q1 inverting output 1. 12 q1 noninverting output 1. 15 v ref 1 reference voltage 1. reference voltage for biasing ac-coupled inputs, channel 1. 16 v t 1 center tap 1. center tap of 100 input resistor, channel 1. heat sink nc no connect. the metallic back surface of the package is no t electrically connected to any part of the circuit. it can be left floating for optimal electrical isolation between the package handle and the substrate of the die. it can also be soldered to the application board if improved thermal and/or mechanical stability is desired. exposed metal at the corners of the package is connected to this back surface. allow sufficient clearance to vias and other components. pin 1 indicator nc = no connect 1d 2d 3 nc 4 nc 11 q1 12 q1 10 q2 9q2 5 n c 6 n c 7 v e e 8 v c c 1 5 v r e f 1 6 v t 1 4 v e e 1 3 v c c adclk925 top view (not to scale) 06318-006 figure 6. adclk925 pin configuration table 6. pin function descriptions for 1:2 adclk925 buffer pin no. mnemonic description 1 d noninverting input. 2 d inverting input. 3, 4, 5, 6 nc no connect. no physical connection to the die. 7, 14 v ee negative supply voltage. 8, 13 v cc positive supply voltage. 9 q2 inverting output 2. 10 q2 noninverting output 2. 11 q1 inverting output 1. 12 q1 noninverting output 1. 15 v ref reference voltage. reference voltage for biasing ac-coupled inputs. 16 v t center tap. center tap of 100 input resistor. heat sink nc no connect. the metallic back surface of the package is no t electrically connected to any part of the circuit. it can be left floating for optimal electrical isolation between the package handle and the substrate of the die. it can also be soldered to the application board if improved thermal and/or mechanical stability is desired. exposed metal at the corners of the package is connected to this back surface. allow sufficient clearance to vias and other components.
ADCLK905/adclk907/adclk925 rev. 0 | page 8 of 16 typical performance characteristics v cc = 3.3 v, v ee = 0.0 v, t a = 25c, outputs terminated 50 to v cc ? 2 v, unless otherwise noted. 06318-007 q q 1.37v 200ps/div 100mv/di v 2.37v figure 7. output waveform, v cc = 3.3 v ? 90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 10 100 1k 10k 100k 1m 10m 100m 06318-008 f (hz) l[f] (dbc/hz) agilent e5500 carrier: 122.88mhz no spurs figure 8. phase noise at 122.88 mhz ? 90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 10 100 1k 10k 100k 1m 10m 100m 0 6318-009 f (hz) l[f] (dbc/hz) agilent e5500 carrier: 245.76mhz no spurs figure 9. phase noise at 245.76 mhz 06318-010 q q 100ps/div 100mv/di v 1.37v 2.37v figure 10. output waveform, v cc = 3.3 v ? 90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 10 100 1k 10k 100k 1m 10m 100m 06318-011 f (hz) l[f] (dbc/hz) agilent e5500 carrier: 622.08mhz no spurs figure 11. phase noise at 622.08 mhz 0 50 100 150 200 250 300 012345678 0 6318-012 input slew rate (v/ns) rms jitter (fs) figure 12. rms jitter vs. input slew rate
ADCLK905/adclk907/adclk925 rev. 0 | page 9 of 16 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1234 ?55c +25c +125c 0 6318-013 supply voltage (v) output swing (v) figure 13. v od vs. power supply voltage 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 3.0 3.5 2.5 4.0 06318-014 power supply voltage (v) power supply current (a) ?55c +25c +125c ?55c +25c +125c figure 14. power supply current vs. power supply voltage, ADCLK905 ?55c +25c +125c 90 95 100 105 110 1.6 2.1 2.6 3.1 3.6 06318-015 input common mode (v) propagation delay (ps) figure 15. propagation delay vs. v icm ; input swing = 200 mv 01234 0 0.01 0.02 0.03 0.04 0.05 0.06 0.09 0.08 0.07 06318-016 supply voltage (v) power supply current (a) ?55c +25c +125c +25c +125c ?55c figure 16. power supply curren t vs. supply voltage, adclk925 94 95 96 97 98 99 100 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 06318-017 v id (v) t pd (ps) figure 17. propagation delay vs. v id 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 06318-018 frequency (ghz) v od (v) figure 18. toggle rate, different ial output swing vs. frequency
ADCLK905/adclk907/adclk925 rev. 0 | page 10 of 16 1 3 58ps/div c4 2 06318-019 17ps/div 1 3 2 c4 06318-023 figure 19. 2.488 gbps prbs 2 23 ? 1 with oc-48/stm-16 mask, measured p-p jitter 8.1 ps, source p-p jitter 3.5 ps figure 22. 8.50 gbps prbs 2 23 ? 1 with fc8500e abs beta rx mask, measured p-p jitter 10.9 ps, source p-p jitter 4.4 ps 15ps/div 2 1 3 c4 06318-022 1 3 2 58ps/div c4 06318-021 figure 20. 9.95 gbps prbs 2 23 ? 1 with oc-193/stm-64 mask, measured p-p jitter 10.5 ps , source p-p jitter 6.0 ps figure 23. 2.5 gbps prbs 2 23 ? 1 with pci express 2.5 rx mask, measured p-p jitter 8.1 ps, source p-p jitter 3.5 ps 34ps/div 1 3 c4 2 06318-020 1 3 2 29ps/div c4 06318-024 figure 21. 4.25 gbps prbs 2 23 ? 1 with fc4250 (optical) mask, measured p-p jitter 8.2 ps, source p-p jitter 3.4 ps figure 24. 5.0 gbps prbs 2 23 ? 1 with pci express 5.0 rx mask, measured p-p jitter 8.7 ps, source p-p jitter 3.5 ps
ADCLK905/adclk907/adclk925 rev. 0 | page 11 of 16 applications information power/ground layout and bypassing the ADCLK905/adclk907/adclk925 buffers are designed for very high speed applications. consequently, high speed design techniques must be used to achieve the specified performance. it is critically important to use low impedance supply planes for both the negative supply (v ee ) and the positive supply (v cc ) planes as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. it is also important to adequately bypass the input and output supplies. a 1 f electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. in addition, multiple high quality 0.001 f bypass capacitors should be placed as close as possible to each of the v ee and v cc supply pins and should be connected to the gnd plane with redundant vias. high frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should be strictly avoided to maximize the effectiveness of the bypass at high frequencies. output stages the specified performance can be achieved only by using proper transmission line terminations. the outputs of the ADCLK905/ adclk907/adclk925 buffers are designed to directly drive 800 mv into 50 cable or microstrip/stripline transmission lines terminated with 50 referenced to v cc ? 2 v. the pecl output stage is shown in figure 25 . the outputs are designed for best transmission line matching. if high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse width- dependent propagation delay dispersion. v ee v cc q q 06318-025 figure 25. simplified schematic diagram of the ADCLK905/adclk907/adclk925 pecl output stage optimizing high speed performance as with any high speed circuit, proper design and layout techniques are essential to obtaining the specified performance. stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and cause oscillation. discontinuities along input and output transmission lines can also severely limit the specified jitter performance by reducing the effective input slew rate. in a 50 environment, input and output matching have a significant impact on performance. the buffer provides internal 50 termination resistors for both d and d inputs. the return side should normally be connected to the reference pin provided. the termination potential should be carefully bypassed, using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. if the inputs are directly coupled to a source, care must be taken to ensure the pins are within the rated input differential and common-mode ranges. if the return is floated, the device exhibits 100 cross termination, but the source must then control the common-mode voltage and supply the input bias currents. there are esd/clamp diodes between the input pins to prevent the application of excessive offsets to the input transistors. esd diodes are not optimized for best ac performance. when a clamp is desired, it is recommended that appropriate external diodes be used. buffer random jitter the ADCLK905/adclk907/adclk925 are specifically designed to minimize added random jitter over a wide input slew rate range. provided sufficient voltage swing is present, random jitter is affected most by the slew rate of the input signal. whenever possible, excessively large input signals should be clamped with fast schottky diodes because attenuators reduce the slew rate. input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics.
ADCLK905/adclk907/adclk925 rev. 0 | page 12 of 16 typical application circuits v ref v cc v t d d 06318-026 connect v t to v cc . figure 26. interfacing to cml inputs v ref v cc ?2v v t d d 06318-028 connect v t to v cc ? 2v. figure 27. interfacing to pecl v ref v t d d 06318-029 notes 1. placing a bypass capacitor from v t to ground can improve the noise performance. connect v t to v ref . figure 28. ac coupling differential signals v ref v t d d 06318-030 connect v t ,v ref , and d. place a bypass capacitor from v t to ground. alternatively, v t ,v ref , and d can be connected, giving a cleaner layout and a 180o phase shift. figure 29. interfacing to ac-c oupled single-ended inputs
ADCLK905/adclk907/adclk925 rev. 0 | page 13 of 16 evaluation board schematic 0 6318-031 val adclk9xx d1 d1 d2 d2 v t 2 q2 q2 q1 q1 pad v ref 2 v ee _7 v cc _8 v cc _13 v ee _14 v ref 1 v t 1 lfcsp16-3x3 solder bridges will be completed by end user if desired. 0 ? resistors are not to be installed. matched length 2 v cc v ref 2 v ref 1 matched lengths matched length 2 v t 2 v t 1 v ee jumpers are not to be installed. solder bridges will be completed by end user if desired. solder bridges will be completed by end user if desired. 0 ? resistors are not to be installed. c45 .01uf v cc c44 .01uf c12 .1uf c11 .1uf c10 .1uf c9 .1uf c16 .1uf c15 .1uf c26 .1uf c14 .1uf c13 .1uf c32 .1uf c33 .1uf c34 .1uf c35 .1uf c31 .1uf c28 .1uf c29 .1uf c30 .1uf c40 .1uf c41 .1uf c42 .1uf c43 .1uf c39 .1uf c38 .1uf c37 .1uf c36 .1uf c17 .1uf c18 .1uf c19 .1uf c20 .1uf c21 .1uf c22 .1uf c23 .1uf c24 .1uf c8 .1uf c7 .1uf c6 .1uf c5 .1uf c4 .1uf c3 .1uf c2 .1uf c1 .1uf c25 2.2uf c27 2.2uf q2_b q2 q1_b q1 d2_b d2 d1_b d1 cal_2 cal_1 1 2 4 3 5 9 10 12 11 pad 6 7 8 13 14 15 16 a1 v t 1 r1 0 r2 0 1 2 jp7 0 1 2 jp1 0 v ref 2 v ref 1 v t 1 v ref 2 v t 2 j12 j4 j3 j6 j5 j2 j1 j7 v ref 2 v ref 1 1 tp5 red 1 tp4 blk 1 tp3 red 1 tp1 blk 1 tp2 red v ee v cc v ee 1 tp8 red j8 j9 j10 j11 v t 2 v ref 1 vt1 1 2 jp2 0 1 2 jp3 0 1 2 jp4 0 1 2 jp5 0 1 2 jp6 0 1 2 jp8 0 1 tp6 red 1 tp7 red v t 2 v ee v cc v ee figure 30. evaluation board schematic
ADCLK905/adclk907/adclk925 rev. 0 | page 14 of 16 outline dimensions 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 31. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-3) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADCLK905bcpz-wp 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y03 ADCLK905bcpz-r7 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y03 ADCLK905bcpz-r2 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y03 adclk907bcpz-wp 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y06 adclk907bcpz-r7 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y06 adclk907bcpz-r2 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y06 adclk925bcpz-wp 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y08 adclk925bcpz-r7 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y08 adclk925bcpz-r2 1 ?40c to +125c 16-lead lfcsp_vq cp-16-3 y08 ADCLK905/pcbz 1 evaluation board adclk907/pcbz 1 evaluation board adclk925/pcbz 1 evaluation board 1 z = rohs compliant part.
ADCLK905/adclk907/adclk925 rev. 0 | page 15 of 16 notes
ADCLK905/adclk907/adclk925 rev. 0 | page 16 of 16 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06318-0-8/07(0)

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